DFT
Free Interview Questions & Answers
What is DFT?
Design for testability is a design technique that modifies a chip such that the testing process becomes easier and more cost-effective by adding extra circuitry to the chip. With the help of DFT techniques, the controllability and observability of the internal fault nodes are improved.
This is where the industry needs test engineers who can generate test vectors after the design is completed. But this approach will consume a substantial amount of time and effort that could be avoided if testing is considered at an early phase in the design flow (i.e.) Integration of design & test called DFT (Design for testability).
Why is DFT important?
Due to development in technology, billions of transistors are being tightly packed in a small tiny chip giving rise to additional challenges, so the chances of defects are also more. Testing is required to ensure the quality of the product. During the fabrication process, several types of defects may exist which may result in the destruction of some of the transistors on the chip.
It is necessary to test each and every chip for its performance and functionality before it is shipped.
How to prepare for the DFT Interviews?
DFT interviews are based on the DFT concepts and DFT tool knowledge.
After you are trained with the DFT concepts, you need to make sure that you have more hands-on experience with the different DFT tools.
Hands-on knowledge in DFT topics like ATPG flow, Scan chain flow, and MBIST flow is highly ne
What is expected from the DFT Interviews?
The interviewer checks your DFT concepts in ATPG, Scan chain, Boundary scan, MBIST, etc. They also expect you to be hands-on with the DFT tools. You should be aware of the following test scenarios:
- DRC violations analysis and fixing the same
- Simulation mismatch debugging
- Test coverage improvem
- Verifies the correctness of the RTL design.
- Responsible for the quality of the RTL design.
- A method integrated with design for improving the controllability & observability of the design.
- Checks & validates the final product.
Answer: c) A method integrated with design for improving the controllability & observability of the design.
Answer: A scan chain is formed by a number of mux-based D flip-flops connected back to back in a chain with the output of one flop connected to another. The flip-flops are called scan cells in the scan-based designs that are used to shift in and shift-out test data.
- After MBIST insertion, a lock-up latch is used between the MBIST controller and the Memory interface.
- Scan chains from different clock domains
- Scan cells within the same clock domains
Answer: b) Scan chains from different clock domains
- Functional verification
- Behavioral level
- Switch level
- Structural level
Answer: c) Switch level, d) Structural level
Answer: c) 14
- DFT library is an RTL code.
- It defines a function of the system-level components
- It defines a function of the lowest-level netlist module.
Answer: c) It defines a function of the lowest-level netlist module.
- True
- False
Answer: a) True
- The MemoryBIST controller didn't complete the test and one or more memories failed
- The MemoryBIST controller completed the test and one or more memories failed
- The MemoryBIST controller didn't complete the test but no memories failed so far
- The MemoryBIST controller completed the test and all memories passed
Answer: b) The MemoryBIST controller completed the test and one or more memories failed.
Answer: 5, TDI, TDO, TCK,TRST, TMS
Conclusion
It’s good to be trained in both Design and testing that is what we call Design for Testability where you learn how to fix RTL design issues and also integrate the DFT techniques into the RTL for making the chip testing easier after the chips are manufactured. We make sure that only good chips are shipped to the customer.
More VLSI interview questions
